Integrated semiconductor memories have a memory cell array having a multiplicity of memory cells connected to word lines and bit lines. In the case of volatile semiconductor memories, in particular DRAMs (dynamic random access memory), each memory cell has a selection transistor and a storage capacitor. The selection transistor is usually a MOSFET (metal oxide semiconductor field effect transistor) having two source/drain regions which are arranged in a semiconductor substrate and between which a transistor channel can be formed. Arranged above the channel region for the transistor channel is a gate dielectric and above that a gate electrode, which forms an interconnect section of the word line to which the memory cell is connected. One of the two source/drain regions is connected to the bit line; the other source/drain region of the selection transistor is conductively connected to a first capacitor electrode of the storage capacitor. In addition to the first capacitor electrode, the storage capacitor furthermore has a second capacitor electrode, which is separated from the first capacitor electrode by a capacitor dielectric. The storage capacitor is usually formed as a trench capacitor arranged within the semiconductor substrate, or as a stacked capacitor arranged outside the semiconductor substrate.
Volatile memory cells formed in this way store digital information in the form of quantities of electrical charge that are stored in the storage capacitor if the selection transistor of the memory cell is turned off. In order to read out the memory information, the selection transistor is turned on and the bit line to which the memory cell is connected is subjected to charge reversal on account of the previously stored charge of the storage capacitor. As a result, the electrical potential of the bit line to which the selection transistor of the memory cell is connected is altered after the selection transistor has been opened. In DRAMs, there are always two bit lines connected to one and the same sense amplifier, also called signal amplifier. The sense amplifier serves for amplifying the difference between the electrical potentials of the two bit lines which are connected to it, that is to say for spreading the difference between the two electrical potentials of the bit lines. In order to read out memory data, firstly the two bits lines are biased with a precharge potential, the level of which usually lies in the middle between a neutral potential and a first potential corresponding to the potential of a bit line that is biased with a digital “1” and thus activated. The precharge potential is often abbreviated to Vbleq and the first potential to Vblh. The neutral potential is a reference potential of, for example, 0 volts (ground potential). A bit line with the aid of which a digital “0” is written to the memory cell when the potentials are spread is biased with the neutral potential. Consequently, the sense amplifier effects an increase in the bit line potential from the precharge potential to the potential Vblh if a digital one is written back, and a decrease in the bit line potential from the precharge potential Vbleq to the neutral potential if a digital zero is written back.
The read-out and spreading of the bit line potential are effected after first of all the word line of the selection transistor is activated and the selection transistor is thereby turned on, so that, on account of the quantity of charge of the storage capacitor that is distributed onto the bit line, an initially slight, but measurable potential difference with respect to the potential of the other bit line connected to the same sense amplifier is produced. The sense amplifier subsequently amplifies the potential difference between the two bit lines. As a result, the storage capacitor of the memory cell is subjected to charge reversal via those bit lines to which the memory cell is connected. The transistor is subsequently turned off again by deactivating the word line and thereby interrupting the formation of the transistor channel.
Integrated semiconductor memories are being fabricated with increasingly miniaturized dimensions of the memory cells and of the rest of the structure elements on the semiconductor substrate in order to obtain a maximum memory cell density per basic substrate area. In particular, the dimensioning of the word lines is being made narrower and the gate lengths are thereby being shortened. As the size of the structure elements of the semiconductor memory is reduced, the required operating voltages of the selection transistors also decrease since the threshold voltage of the selection transistor decreases as the gate length decreases. The reduction of the operating voltage of the selection transistors accords with the requirement for reducing the current consumption of the semiconductor memory. However, it is not possible to miniaturize the transistors contained in the sense amplifier to the same extent as the selection transistors of the memory cells. One reason for this is that the sense amplifier is used to generate a voltage boost that requires the transistors of the sense amplifier to have larger dimensions. Therefore, the operating voltage of the sense amplifier cannot be lowered in the same way as that of the selection transistors.
In the case of so called “mid-level sensing”, in which the bit lines are biased, prior to the opening of the selection transistors, with a precharge potential lying precisely in the middle between a first bit line potential corresponding to a digital “1” and a second bit line potential corresponding to a digital “0”, the quantity of charge required for the charge reversal of the bit line, that is to say the current consumption, is particularly low. This is due to the fact that the potential Vblh for an activated bit line, which corresponds to a digital “1” and the neutral potential of a bit line, which corresponds to a digital “0”, in each case have the same potential difference with respect to the precharge potential Vbleq. Therefore, the same quantity of charge is required for writing a digital zero to the memory cell read first of all and for writing a digital one.
However, if the selection transistors of the memory cells are provided with smaller dimensions than those of the sense amplifiers and are additionally operated with smaller operating voltages, then the threshold voltage of the transistors of the sense amplifier and hence the operating point of the sense amplifier is greater than the precharge potential Vbleq of the selection transistors, at least when using mid-level sensing. If the selection transistors are biased with the precharge potential prior to the read-out, the sense amplifier is then no longer operated at its optimum operating point, but rather with a smaller voltage in comparison therewith. As a result, the evaluation of the bit line signals takes longer and a larger spreading, that is to say a larger voltage amplification by the signal amplifier is required than if the signal amplifier were operated at a voltage corresponding to its operating point.
A further problem of present-day semiconductor memories consists in the fact that in a sense amplifier, transistors whose operating point corresponds to a higher voltage than the potential Vbleq of the selection transistors operated with mid-level sensing, the switching signal for writing back a digital one (corresponding to the bit line potential Vblh) becomes weaker. This is because if the operating point of the sense amplifier is greater than the precharge potential Vbleq, the potential difference between the operating point of the sense amplifier and the potential Vblh is smaller. Although in return the signal for writing back a digital zero is all the larger, sufficiently fast programming of the two data values zero and one nonetheless requires a sufficiently high signal strength.